1. Field of Invention
The present invention relates to a method of increasing the yield of semiconductor manufacturing. More particularly, the present invention relates to a method of boosting wafer cleaning efficiency and increasing process yield.
2. Description of Related Art
In integrated circuit manufacturing, the most frequently conducted process includes wafer cleaning. Wafer cleaning is an important process that takes up roughly 30% of the time required to build a product. Wafers must be frequently cleaned just to reduce the amount of impurity particles, contaminants and micro dust particles on the surface of a wafer. If these impurities, contaminants and dust particles are allowed to stay on the wafer surface, the semiconductor devices ultimately formed may have a relatively large leakage current and a relatively low breakdown voltage. In some cases, circuit shorting may occur. Consequently, how to boost wafer cleaning efficiency and increase process yield is an important issue in semiconductor production.
In conventional semiconductor manufacturing, a step called particle calibration is often conducted to estimate the efficiency after a wafer cleaning operation. The calibration is conducted using a laser scanner. To perform a calibration, standard polystyrene latex particles fabricated into different dimensions are scanned to obtain a standard curve. Thereafter, the same laser scanner is used to scan the surface of a wafer and find out size of the particles on the wafer by comparing with the standard curve. However, in practice, particles on the wafer have material properties, shape and sizes very different from the polystyrene latex particles. Therefore, the size of the particles estimated by this method is highly inaccurate and judgment of the wafer cleaning process is imprecise.
In addition, particle dimension as well as particle shape may have some significant effect on the device such as the capacity to resist circuit shorting or some other adverse conditions. For example, if the particles produced by a manufacturing step are deposited in the area between two neighboring conductive patterns, the likelihood of having anomalous conduction between the conductive patterns will be increased significantly. Consequently, design rules must be carefully set to minimize the effect of loose particles on device performance.
Accordingly, one object of the present invention is to provide a method of boosting wafer-cleaning efficiency by providing an accurate assessment of a particular cleaning operation.
A second object of this invention is to provide a method of increasing the process yield of a semiconductor device by simulating the possible size and shape of particles produced in a processing operation so that only processes having no adverse effect on the device are chosen.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of boosting wafer-cleaning efficiency. First, different types of process particles are deposited on the surface of a test wafer. Each type of the process particles has a different material property, dimension and/or shape. Furthermore, the location of each type of process particle on the test wafer is positioned according to design. Thereafter, a cleaning operation is conducted to remove particles from the test wafer. The test wafer is scanned by a scanning tool to determine which types of the process particles on the test wafer are completely removed and which types of the process particles are retained. The resulting data, including the shape and dimension of the process particles retained on the test wafer, are registered. Thus, by scanning the test wafer to obtain data, an accurate assessment of the cleaning capacity of a particular cleaning operation is produced. Finally, according to the test data, parameters used in the cleaning operation are modified to improve cleaning efficiency.
This invention also provides a method of improving process yield of a semiconductor device. First, different types of process particles are deposited on a test wafer. Each type of the process particles has a different material property, dimension and/or shape. Furthermore, the location of each type of the process particles on the test wafer is positioned according to design. Thereafter, the process particles on the test wafer are scanned to simulate the type of possible particles generated in an actual processing operation. Using the data obtained through the scanning operation, including the shape and dimension of each type of the process particles, an accurate assessment of the effect of process particles generated in an actual processing operation on the device is produced. If the results indicate that the particles generated in a particular process adversely affect the device, processing parameters may be modified to increase the production yield.
According to the method of boosting wafer-cleaning efficiency, the size of process particles retained after a particular cleaning operation is accurately determined. Since the capacity of a cleaning operation for removing a particular type of the process particles can be gauged with high precision, wafer-cleaning efficiency can be optimized.
According to the method of increasing process yield, a simulation of an actual processing operation is conducted to find all possible process particles that may be generated. Through the result of simulation, possible effects of process particles on the device can be accurately assessed and hence the process yield can be improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.